Commutation cells are commonly used in electronic systems that require conversion of a voltage source, including both DC-DC converters and DC-AC converters, which are often called inverters. With the limited space allowed for power converter circuits, such as those used for example in electric and/or electric hybrid automotive applications, and given the high cost of the semi-conductors, the demand for integration of these commutation cells increases.
A known way of reducing the space occupied by semiconductors in power converter circuits is to increase their efficiency to allow the size of the cooling surface to be reduced.
Losses in power electronic switches present in conventional power converter circuits are mainly caused by two sources; conduction losses and switching losses. One way to reduce switching losses is generally by accelerating turn-on and turn-off of the power electronic switches. However, fast turn-off of the power electronic switches induces overvoltage in stray inductances of their high-frequency loop. It is thus often required to slow down turning off of the power electronic switches to protect them against overvoltage. This may seriously impact the overall efficiency of conventional power converter circuits.
FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits. A commutation cell 10 converts a DC voltage Vbus from a voltage source 12 (or from a capacitor) into a current source Iout (or into an inductance) that usually generates a voltage Vout appropriate for a load 14 connected to a positive tab of the voltage source 12, the load 14 being for example a resistive load, an electric motor, and the like. The commutation cell 10 comprises a freewheel diode 16 and a controlled power electronic switch 18, for example an isolated gate bipolar transistor (IGBT). A capacitor 20 (Cin) is used to limit variations of the voltage Vbus of the voltage source 12 and an inductance Lout 32 is used to limit the variations of the output current Iout. A gate driver (not shown in FIG. 1 but shown on later Figures) controls turning on and off of the power electronic switch 18. FIG. 1 illustrates a configuration of the commutation cell 10, of the load 14, and of the voltage source 12, in which energy flows from the voltage source 12 to the load 14, i.e. from left to right on the drawing. The commutation cell 10 can also be used in a reverse configuration in which energy flows in the opposite direction, in which case the load 14 is connected between the output inductance Lout 32 and a negative tab of the voltage source 12.
When turned on (i.e. closing), the power electronic switch 18 allows current to pass therethrough, from its collector 22 to its emitter 24; at that time, the power electronic switch 18 can be approximated as a closed circuit. When turned off (i.e. opening), the power electronic switch 18 does not allow current to pass therethrough and becomes an open circuit.
The gate driver applies a variable control voltage between the gate 26 and the emitter 24 of the power electronic switch 18. For some types of power electronic switches such as bipolar transistors, the gate driver may act as a current source instead of as a voltage source. Generally, when the voltage applied between the gate 26 and the emitter 24 is “high”, the power electronic switch 18 allows passing of current from the collector 22 to the emitter 24. When the voltage applied between the gate 26 and the emitter 24 is “low”, the power electronic switch 18 blocks passage of current therethrough. In more details, a voltage difference between the gate 26 and the emitter 24, denoted Vge, is controlled by the gate driver. When Vge is greater than a threshold Vge(th) for the power electronic switch 18, the switch 18 is turned on and a voltage Vce between the collector 22 and the emitter 24 becomes near zero. When Vge is lower than Vge(th), the power electronic switch 18 is turned off and Vge eventually reaches Vbus.
When the power electronic switch 18 is turned on, a current Iout flows from the voltage source 12 (and transiently from the capacitor 20) through the load 14 and through the collector 22 and the emitter 24. When the power electronic switch 18 is turned off, the current Iout circulates from the load 14 and passes in the freewheel diode 16. It may thus be observed that the power electronic switch 18 and the freewheel diode 16 operate in tandem. Turning on and off of the power electronic switch 18 at a high frequency allows the current Iout, in the output inductance Lout 32, to remain fairly constant.
It should be observed that, in the case of other power electronic switch types, for example bipolar transistors, the term “gate” may be replaced with “base”, the base being controlled by a current as opposed to the gate that is controlled by a voltage. These distinctions, well known to those skilled in the art, do not change the overall operation principles of the commutation cell 10.
FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1, showing parasitic (stray) inductances. In contrast with the idealized model of FIG. 1, connections between components of an actual commutation cell define parasitic inductances. Though the parasitic inductances are distributed at various places within the commutation cell 10, a suitable model presented in FIG. 2 shows two (2) distinct inductances representing the overall parasitic inductance, including an emitter inductance 30 of the power electronic switch 18 and an inductance 34 representative of all other parasitic inductances (other than the emitter inductance 30) around a high frequency loop 36 formed by the freewheel diode 16, the power electronic switch 18 and the capacitor 20. The high frequency loop 36 is a path where current changes significantly upon switching of the power electronic switch 18. It should be noted that an output inductance Lout 32 is not part of the high frequency loop 36 because its current remains fairly constant through the commutation period.
FIG. 3 is a circuit diagram of a conventional commutation cell further showing a gate driver 40. Some elements of the commutation cell 10 are not shown on FIG. 3, in order to simplify the illustration. FIG. 3 shows a gate driver 40 having a positive supply voltage 42, a negative supply voltage 44 and an output 46 being connected to the gate 26 of the power electronic switch 18 via a gate resistor Rg. The positive supply voltage 42 of the gate driver 40 has a value denoted +Vcc, for example +15 volts above a ground reference (shown on a later Figure) while the negative supply voltage 44 has value denoted −Vdd, for example −5 volts below the ground reference. A ground reference of the gate driver 40 is connected to the emitter 24 of the power electronic switch 18; this connection is not shown on FIG. 3. An input 50 of the gate driver 40 is connected to a controller (not shown) of the commutation cell 10, as is well known in the art. A voltage at the output 46 of the gate driver 40 goes up to +Vcc and goes down to −Vdd in order to control the voltage at the gate 26. The input resistance of the gate 26 to emitter may be very high, especially in the case where the electronic switch 18 is an IGBT. However, a parasitic capacitance Cge (shown on a later Figure), present between the gate 26 and the emitter 24 and a parasitic Miller capacitance Cgc (not shown), present between the gate 26 and the collector 22, for a total gate equivalent capacitor Cies, causes some current to flow from the output 46 when the gate driver 40 alternates between +Vcc and −Vdd. The value Rg of the gate resistor is selected as a function of the parasitic capacitance Cies and of a desired switching rate of the power electronic switch 18 so that the voltage at the gate 26 changes at a rate appropriate for the desired switching rate.
On FIG. 3, a current Iigbt flowing through the power electronic switch 18 and through the emitter parasitic inductance 30 is essentially equal to Iout when the power electronic switch 18 is closed, and quickly reduces to substantially zero when the power electronic switch 18 turns off.
When the power electronic switch 18 turns on or off, the current Iigbt flowing therethrough increases or diminishes at a fast rate. These variations of Iigbt, denoted di/dt, induce voltage across inductances 30 and 34, according to the well-known equation (1):
                              V          L                =                  L          ·                      di            dt                                              (        1        )            
wherein VL is a voltage induced across an inductance and L is an inductance value.
A voltage VL, is induced across the parasitic inductance 34 and a voltage VLe is induced across the emitter parasitic inductance 30. On FIGS. 2 and 3, the polarities shown across the inductances of the high frequency loop 36, including the emitter inductance 30, reflect voltages obtained upon turn-off of the power electronic switch 18, when the Iigbt current diminishes very rapidly, di/dt thus taking a negative value. Upon turn-on of the power electronic switch 18, voltages across the inductances of the high frequency loop 36, including the emitter inductance 30, are in the opposite direction.
These voltages VLs and VLe are in series with Vbus from the voltage source 12. When the power electronic switch 18 turns off, the collector 22 to emitter 24 voltage increases until the freewheel diode 16 turns on. At that time, addition of Vbus, VLs and VLe results in an important overvoltage applied between the collector 22 and the emitter 24 of the power electronic switch 18. Though power electronic switches are rated for operation at some level of overvoltage, extreme overvoltage can reduce the lifetime of any power electronic switch to thereby lead to its premature failure.
FIG. 4 is a circuit diagram of an IGBT leg having resistive dividers connected across parasitic (stray) emitter inductances, forming compensation circuits. The circuit of FIG. 4 was introduced in International Patent Publication No. WO 2014/161080 A1 to Jean-Marc Cyr et al., published on Oct. 9, 2014, the disclosure of which is incorporated by reference herein.
Generally, FIG. 4 shows a power converter having a pair of commutation cells connected in parallel, each commutation cell including a power electronic switch and a gate driver. The power converter may for example be an IGBT leg 90 including compensation circuits connected to gate drivers in a configuration that reduces overvoltage on the IGBTs. The IGBT leg 90 may for example form one third of a three-phase alternative current (AC) power source driving an electric motor (not shown) from battery 12. The IGBT leg 90 feeds a current source Iout via an inductance Lout through a phase tab (not shown) connected between top and bottom power electronic switches, the phase tab having a parasitic inductance Lphase. FIG. 4 introduces compensation circuits that optimize overvoltage on the IGBT using a resistive divider across the emitter parasitic inductance.
The IGBT leg 90 comprises a top commutation cell including a top IGBT Q2 and a bottom freewheel diode D1. The top IGBT Q2 is driven by a gate driver 62 connected to a gate 64 of the top IGBT Q2 via a resistor R4. A top compensation circuit includes a turn-on diode D4 and resistors R5 and R6. In the IGBT leg 90, a bottom commutation cell includes a bottom IGBT Q1 and a top freewheel diode D2. The bottom IGBT Q1 is driven by a gate driver 60 connected to a gate 26 of the bottom IGBT Q1 via a resistor R1. A bottom compensation circuit includes a turn-on diode D3 and resistors R2 and R3. The top commutation cell operates when Iout is positive (in the direction shown in FIG. 4) and the bottom commutation cell operates when Iout is in the opposite direction.
Components of the IGBT leg 90 are placed on a power module (not shown) having a positive voltage tab connected to +Vbus, a negative voltage tab connected to −Vbus (also not shown) and a phase voltage tab connected to Lout. Connections between these components create a number of parasitic inductances, including a parasitic positive voltage tab L+Vbus, a parasitic top collector inductance Lc-high, a parasitic top emitter inductance Le-high, a parasitic bottom collector inductance Lc-low, a parasitic bottom emitter inductance Le-low, a parasitic negative voltage tab inductance L−bus and input capacitor inductance Lc. The two commutation cells combine with an input capacitance Cin of a voltage source 12 to form a high frequency loop 92 of the IGBT leg 90.
Discussing the bottom commutation cell of the IGBT leg 90 of FIG. 4, the gate 26 of the bottom IGBT Q1 connected to its gate driver 60 via the resistor R1. A ground reference 52 of the gate driver 60 (GND low) is connected to a bottom compensation circuit having a resistive divider circuit including the two resistors R2 and R3 and the turn-on diode D3, which allows the turn-on not to be impacted by the resistive divider by keeping the voltage at the emitter of the bottom IGBT Q1 not lower than the ground reference 52. The turn-on diode D3 is conducting while turning on the bottom IGBT Q1 because the direction of its current in positive. In contrast, the turn-on diode D3 is not conducting while turning off the bottom IGBT Q1 because of the voltage induced across the emitter inductance during the di/dt applies a negative voltage across the turn-on diode D3.
In the circuit of FIG. 4, values of the resistors R2 and R3 are selected according to an acceptable overvoltage level allowed across the bottom IGBT Q1. A ratio of R2 over R3 is increased to reduce the overvoltage. The value of the equivalent gate resistor is set with these two resistors R2 and R3 in parallel, in series with a gate driver resistor R1. A value of the gate driver resistor R1 is adjusted in a conventional manner according to a proper commutation behavior.
In other words, the normal practice consisting in using a resistor R1 in the ground connection of the gate driver to limit the current in the diodes that protect the gate driver 60 of the bottom IGBT Q1 from a negative voltage when the top IGBT Q2 turns off has been modified by splitting the resistor in two resistors, including R1 in series with R2 and R3 connected in parallel, and by adapting their ratio to limit the effect of the emitter inductance on the di/dt. An equivalent resistor value may remain the same, but the voltage divider gives the desired weight of the emitter inductance to limit the overvoltage at the desired level.
By correctly setting values of the resistors of the compensation circuits, it is possible to reduce the effect of the emitter inductance to get the maximum overvoltage allowed to therefore improve the efficiency.
The overvoltage can be optimized as much as possible to reach the maximum IGBT rating while maintaining the speed of the di/dt for efficiency reasons. This is done by reducing a value of R2, the resistor connected to the IGBT emitter, compared to R3, the resistor connected to the power tab. The voltage across the emitter inductance is thus split in two parts and only the part of the voltage across R2 is applied in the gate drive circuit to limit the gate voltage drop.
The values of the resistors R2 and R3 are selected according to the level of overvoltage allowed across Q1. FIG. 5 is a diagram showing turn-off waveforms of the bottom IGBT of FIG. 4. In more details, FIG. 5 show the result of a resistive divider optimized for an operation at a bus voltage Vbus of 500 Vdc. The ratio of R2 over R3 can be increased to reduce the overvoltage. The equivalent value of the two resistors R2 and R3, in parallel, is set in series with R1, which is adjusted according to the proper commutation behavior of the bottom IGBT Q1. By setting the resistor values correctly, it is possible to reduce the effect of the emitter inductance to get the maximum overvoltage allowed on the bottom IGBT Q1 to therefore improve the efficiency.
The collector to emitter overvoltage may be optimized as much as possible to reach the maximum voltage rating of the bottom IGBT Q1. This is done by reducing a value of the resistor R2 connected to the logical emitter of the bottom IGBT Q1 compared to a value of the resistor R3 connected to the power tab. The voltage across the emitter inductance Le-low, alone or with the negative voltage tab inductance L−Vbus, is split in two parts and only the voltage across the resistor R2 is applied at the reference 52 of the gate driver 60 to limit the voltage drop at the gate 26 of the bottom IGBT Q1.
FIG. 5 shows the current Ligbt, the gate to emitter voltage Vge and the collector to emitter voltage Vce during turn-off of the bottom IGBT Q1 of FIG. 4. It is notable that Vce peaks at a plateau 80 whose value is tailored according to the maximum voltage rating of the bottom IGBT Q1. This plateau 80 occurs while the rate of drop of Vge is contained at area 82 by the insertion of the voltage sample from the parasitic inductances Le-low and L−Vbus.
FIG. 6 is a circuit diagram in which the compensation circuits of FIG. 4 are modified to impact the turn-on of the IGBTs. A variant of the circuit of FIG. 6 was introduced in U.S. Provisional Patent Application Ser. No. 62/183,437 to Jean-Marc Cyr et al., filed on Jun. 23, 2015, the disclosure of which is incorporated by reference herein.
Generally, FIG. 6 shows a modified IGBT leg 95 in which the ground reference 52 (GND low) is now electrically connected to the emitter 24 of the bottom IGBT Q1 via the turn-on diode D3 placed in series with a resistor RD3. The turn-on diode D3 is polarized to become short when an emitter voltage of the bottom IGBT Q1 is higher than a voltage of the ground reference 52. The ground reference 52 is also electrically connected across both parasitic inductances Le-low and L−Vbus via the resistor R2 and R3. The resistor R2 is placed in parallel with the series combination of the turn-on diode D3 and of the resistor RD3. If the resistor RD3 is replaced by a short circuit, there is no compensation at turn-on and the IGBT leg 95 becomes equivalent to the IGBT leg 90, at least for the bottom compensation circuit. In the presence of the turn-on diode D3, selection of a proper value for the resistor RD3 allows to fine tune the turn-on of the bottom IGBT Q1 independently from its turn-off, the bottom compensation circuit forming a resistive divider between RD3 in parallel with R2, this parallel combination being in series with R3.
A ground reference 54 (GND high) is electrically connected to the emitter of the top IGBT Q2, via the turn-on diode D4 placed in series with a resistor RD4. Turn-on diode D4 is polarized to become short when an emitter voltage of the top IGBT Q2 is higher than a voltage of the ground reference 54. The ground reference 54 is also electrically connected to collector 22 of the bottom IGBT Q1 via the resistor R6. The resistor R5 is placed in parallel with the series combination of the turn-on diode D4 and of the resistor RD4. In the presence of the turn-on diode D4, selection of a proper value for the resistor RD4 allows to fine tune the turn-on of the top IGBT Q2 independently from its turn-off, the top compensation circuit forming a resistive divider between RD4 in parallel with R5, this parallel combination being in series with R6.
Considering the IGBT leg 90 of FIG. 4 and the IGBT leg 95 of FIG. 6, the top and bottom compensation circuits operate in similar ways. However, in a typical implementation, the emitter inductance Le-high of the top IGBT Q2 is smaller than the emitter inductance Le-low of the bottom IGBT Q1. Though the collector inductance Lc-low of the bottom IGBT Q1 can be combined with the emitter inductance Le-high of the top IGBT Q2, FIGS. 4 and 6 showing that the resistor R6 is connected between the emitter inductance Le-high of the top IGBT Q2 and the collector inductance Lc-low of the bottom IGBT Q1, this combination is still smaller than the combination of the negative voltage tab inductance L−Vbus with the emitter inductance Le-low. For that reason, though the top and bottom commutation cells of the IGBT legs 90 and 95 are constructed in the same manner, their behavior is somewhat different. While the above-described techniques work very well for the bottom IGBT Q1, the emitter inductance Le-high is often too small to suitably clamp a voltage thereacross without increasing the gate resistor R4 to protect the device. In fact, in practice, the emitter inductance Le-high of the top IGBT Q2 in series with the collector inductance Lc-low of the bottom IGBT Q1, is oftentimes too low to be used to limit the overvoltage across the top IGBT Q2 at the desired level.
Therefore, there is a need for improvements in circuits capable of reducing overvoltage occurring upon switching in a power converter.